Various means of electrically and mechanically connecting, or coupling, an integrated circuit (IC) chip to a major substrate, are known. One means used for this purpose is to employ an intermediate substrate, sometimes called an interposer, positioned between the IC chip and the major substrate. Such interposers are generally used to provide a number of low-impedance paths for power and ground voltages to the IC chip from the major substrate, which cannot be achieved with wire bonds or lead frames. Optionally, a capacitor may be incorporated onto the interposer and coupled between a selected power line and ground to reduce the amount of noise generated on the power line due to simultaneous digital switching events occurring in the IC chip circuitry. Signal lines to the IC chip may be formed in the interposer, or may be provided by a lead frame or other suitable coupling means.
One type of interposer, as shown at 5 in FIG. 1 in a cross-sectional view, comprises a rigid substrate 6 (e.g., ceramic), a plurality of conductive vias 7 formed through substrate 6, a plurality of conductive pads 8 disposed on the interposer's top surface, each pad 8 positioned over a corresponding via 7, and a set of conductive pads 9 disposed on the interposer's bottom surface in a similar manner. Each via 7 and its corresponding pads 8 and 9 collectively form a vertical connector. The IC chip, shown at 1 in FIG. 1, has a plurality of pads 2 disposed on its active surface in corresponding relationship to pads 8 on the interposer's top surface. Likewise, the major substrate, shown at 3, has a plurality of pads 4 disposed on its surface in corresponding relationship to pads 9 on the interposer's bottom surface.
For electrical coupling, a plurality of solder bumps are typically disposed on the pads of either the IC chip or the interposer'stop surface (or on both sets of pads). Likewise, a second plurality of solder bumps are typically disposed on the pads of either the major substrate or the interposer's bottom surface (or on both sets of pads). The interposer is then brought into alignment and initial contact with the IC chip and major substrate such that corresponding pads are aligned and separated by a corresponding solder bump. The solder bumps are then reflowed by heat to wet and make an adhesive and electrical contact with their corresponding pads. The reflow allows each solder bump to independently change its dimensions so at to compensate for any height variations which may be caused by warpage in the interposer's substrate, the IC chip, or the major substrate, or which may be caused by size variations in the solder bumps. For each of the interposer, IC chip, and major substrate, warpage may cause a 2 .mu.m (micron) to 4 .mu.m height difference between the high and low spots within a .about. 1.0 square centimeter area thereof. Accordingly, for a one centimeter square chip, there may be up to a 4 .mu.m to 8 .mu.m variation in the spacing between the interposer and the IC chip when they are brought into contact. The solder bumps are generally made large enough to compensate for such height variations.
The above-described type of interposer has a number of limitations which discourage its use for high-performance IC chips. First, such IC chips often consume large amounts of power, which raises the temperatures of the chips, causing their dimensions to expand. The thermally induced expansion generates mechanical stresses between the IC chip and the interposer and, as the interposer heats up, stresses between the interposer and the major substrate. These stresses may be sufficient to cause weak solder bumps to break away from their corresponding pads, resulting in a loss of electrical connection. Additionally, as the system undergoes thermal cycling, repeated stress can cause metal fatigue leading to failure of one or more of the bump/pad joints which couple the chip, interposer, and supporting substrate to one another. One prior art way of mitigating the mechanical stresses is to construct the interposer from a material which has a coefficient of thermal expansion (CTE) near that of the IC chip. However, mechanical stresses may still occur between the interposer and the chip each time the IC chip is "powered-up" if a large transient temperature difference develops between the IC chip and the interposer during start up. Additionally, a similar thermal transient may occur between the interposer and the major substrate.
In addition, because of its relatively large surface area, a typical high performance IC chip often has a large warpage across its active surface. If large enough, this warpage can prevent one or more solder bumps from contacting corresponding pads. The chance of contact failure increases as the combined warpage of the IC chip and interposer increases. Additionally, the combined warpages cause variations in the heights and widths of the solder bumps, which in turn causes the thermally-induced mechanical stresses to concentrate at a relatively small number of solder bumps, particularly those with low aspect ratios. This concentration increases the chance of a solder bump failing. Similar warpage effects occur for the interface between the interposer and major substrate. To minimize the warpage effects for both interfaces of the interposer, and thereby minimize the chances of a solder bump failure occurring at either of the interfaces, the interposer should have the smallest possible warpage. Unfortunately, with current manufacturing processes, the yield of interposers with low-warpage decreases as the size of interposers increases, thereby increasing the cost of manufacturing them.
The above-described type of interposer is generally limited in the density of bump/pad connections it may have, typically 100 to 400 per square centimeter. As circuit integration levels for IC chips increases, it is projected that interposers will need a higher density of interconnects, such as for example 2,000 to 10,000 per square centimeter. However, the risk of a bump failure occurring in response to thermally induced stress increases as the number of bumps (i.e., interconnects) increases.
Additionally, due to various limitations in processing the relative thick substrates of typical prior art interposers, the minimum diameter of vias of these interposers and the minimum separation between vias is generally limited to relatively large values. For example, current commercial ceramic processes can achieve, at best, a minimum via diameter of approximately 100 .mu.m (4 mils) and a minimum center separation distance of approximately 150 .mu.m (6 mils), which limits the maximum connector density to 4,400 per square centimeter. This interconnect density is less than the above projected density of 10,000.
To address some of the above-described limitations, other types of interposers using flexible substrates have been recently developed. These interposers generally have a flexible polymer film with a thickness of 250 .mu.m-1000 .mu.m or more, and plurality of through holes drilled, punched, or laser ablated through the film. In some such interposers, a short wire column, or pin, is inserted into each through hole; in others, a layer of metal is electroplated within each through hole. Unfortunately, these interposers have disadvantages associated with the flexible film. Specifically, because of its flexibility, the film often moves, twists, and stretches when being attached to the IC chip and major substrate. Accordingly, the film does not readily preserve the alignment of the through holes to the corresponding pads. To solve this problem, the areas of the pads and the spacing distance between through holes is increased, thereby decreasing the density of interconnects. Moreover, the pins used to fill the through holes sometimes fall out when the film is handled, or when the film is being positioned for contact. When drilling or punching are used to form the through holes, the minimum diameter of the through holes is limited to approximately 250 .mu.m to 500 .mu.m.
In addition to the above interconnect issues, many high performance IC chips require at least one power supply which can supply large transient currents, as for example caused by simultaneous switching of digital circuity, without a significant change in the voltage it provides to the IC chip. One way of accommodating large transient currents is to couple a low inductance, high-value bypass capacitor between the power supply and a reference potential (e.g., ground), placing the bypass capacitor as close to the IC chip as possible. Many rigid, ceramic-substrate interposers incorporate bypass capacitors within their substrates. However, such a capacitor generally occupies a relatively large area, which would prevent the incorporation of many such capacitors on the same interposer unless more layers were added to the interposer, at a further cost, to distribute the capacitors over several layers. To the inventors' knowledge, many, if not all, flexible film interposers do not incorporate bypass capacitors. It is believed that the incorporation of bypass capacitors on such interposers would present major fabrication issues which the art has not heretofore addressed.
Accordingly, there is a need in the art to decrease the failure rate of interconnections of interposers due to thermally-induced mechanical stress and strain, and thereby increase the reliability of interposers and like devices.
There is a further need in the art for a cost effective method of minimizing the warpage of interposers, and of minimizing the deleterious effects caused by warpages in the IC chip, interposer, and major substrate.
There is a yet a further need in the art to increase the density of electrical interconnects of interposers and like devices.
There is a further need to have a high-value bypass capacitance integrated on the interposer, or interconnect structure, along with the large number of interconnects.